With the increase in speed, complexity and integration density of semiconductor circuits, gold has become a preferred conductor material due to its high conductivity and immunity to electromigration effects. In multilevel interconnect patterns through which regions in an underlying substrate are connected to each other and to external terminal pads, silicon dioxide is commonly used as a preferred dielectric material for insulating the gold interconnect lines from each other and from regions in the substrate over which the lines pass. Unfortunately, gold does not readily adhere to silicon dioxide, which leads to the problem of delamination of the interconnect structure, particularly as the dimensions of the integrated circuit become smaller and smaller, thereby effectively reducing the volume of gold relative to its available surface area for contact with the silicon dioxide.
One conventional approach in dealing with the nonadhesion of a gold/silicon dioxide interface has been to consider the problem as insignificant and simply ignore it, as in the case of large scale bipolar circuitry where charge trapping sites are not considered detrimental. Also, since gold lines adhere to underlying oxide through the use of a sputtered, evaporated, or other vacuum deposited overlay, the adhesion on the top and two sides of gold line is not considered to be critical. However, as lateral dimensions of the gold lines continue to shrink, while the vertical dimension, or thickness, of the gold lines remains relatively unchanged, the above-mentioned volume/surface area ratio decreases dramatically, so that the non-adhesion problem can no longer be considered to be insignificant.
In other interconnect configurations, such as those employing aluminum or polysilicon as the interconnect material, the nonadhesion problem of gold is not a consideration. However, neither of these materials (i.e. aluminum and polysilicon) possesses the stable conductive properties required, so that they introduce problems of their own.
Alternatively, it has been proposed to use a different dielectric insulator (usually silicon nitride). Like the proposed substitution of different conductor materials, this approach introduces another set of problems, including the fact that the resulting silicon oxide-silicon nitride interfaces can lead to charge trapping sites, thereby degrading device performance, particularly in the case of CMOS circuitry.